芯驿电子科技（上海）有限公司 基于XILINX ZYNQ7000开发平台的开发板（型号：AX7350B）2022款正式发布了正式发布了，为了让您对此开发平台可以快速了解，我们编写了此用户手册。 这款ZYNQ7000 FPGA开发平台使用XILINX的Zynq7000 SOC 芯片XC7Z035的解决方案，它采用ARM+FPGA SOC技术将双核ARM Cortex-A9 和FPGA 可编程逻辑集成在一颗芯片上。ZYNQ的PS端和PL端各挂载了2片512MB的高速DDR3 SDRAM芯片，另外PS端有1片8GB的eMMC存储芯片和1片256Mb的QSPI FLASH芯片。 外围电路方面我们为用户扩展了丰富的接口，比如1个PCIex4 接槽、2路光纤接口、2路千兆以太网接口、4路USB2.0 HOST接口、、1路HDMI输出接口，1路UART串口接口、1路SD卡接口、一个FMC扩展接口等等。满足用户各种高速数据交换，数据存储，视频传输处理以及工业控制的要求，是一款"专业级“的ZYNQ开发平台。为高速数据传输和交换，数据处理的前期验证和后期应用提供了可能。相信这样的一款产品非常适合从事ZYNQ开发的学生、工程师等群体。 .. image:: images/media/image2.png 开发板简介 ========== 在这里，对这款AX7350B ZYNQ开发平台进行简单的功能介绍。 开发板主要由ZYNQ 7Z035主芯片，4个DDR3，1片eMMC，1个QSPI FLASH和一些外设接口组成。ZYNQ 7Z035采用Xilinx公司的Zynq7000系列的芯片，型号为XC7Z035-2FFG676。ZYNQ7Z035芯片可分成处理器系统部分Processor System（PS）和可编程逻辑部分Programmable Logic（PL）。在ZYNQ7350芯片的PS端和PL端分别挂了2片DDR3，每片DDR3容量高达512M字节，使得ARM系统和FPGA系统能独立处理和存储的数据的功能。PS端的8GB eMMC FLASH存储芯片和256Mb的QSPI FLASH用来静态存储ZYNQ的操作系统、文件系统及用户数据。 AX7350B开发板扩展了丰富的外围接口，其中包含1个PCIex4插槽、2路光纤接口、2路千兆以太网接口、4路USB2.0 HOST接口、1路HDMI输出接口，1路UART串口接口、1路SD卡接口、1个FMC扩展接口和一些按键LED。 下图为整个开发系统的结构示意图： .. image:: images/media/image3.png 通过这个示意图，我们可以看到，我们这个开发平台所能含有的接口和功能。 - Xilinx ARM+FPGA芯片Zynq-7000 XC7Z035-2FFG676。 - DDR3 带有四片大容量的512M字节（共2GB）高速DDR3 SDRAM。其中两片挂载在PS端，可作为ZYNQ芯片数据的缓存，也可以作为操作系统运行的内存; 另外两片挂在PL端，可作为FPGA的数据存储，图像分析缓存，数据处理。 - eMMC PS端挂载一片8GB eMMC FLASH存储芯片，用户存储操作系统文件或者其他用户数据。 - QSPI FLASH 一片256Mbit的QSPI FLASH存储芯片, 可用作ZYNQ芯片的Uboot文件，系统文件和用户数据的存储; - PCIe 2.0 x4接口 一路标准的PCIEx8的主机插槽用于PCIE2.0 x4通信, 可用于连接PCIE2.0 x4, x2, x1的PCIE板卡，实现PCIE数据通信。支持PCI Express 2.0标准，单通道通信速率可高达5GBaud。 - 2路SFP光纤接口 ZYNQ的GTX收发器的2路高速收发器连接到2个光模块的发送和接收，实现2路高速的光纤通信接口。每路的光纤数据通信接收和发送的速度高达10Gb/s。 - 千兆以太网接口 2路10/100M/1000M以太网RJ45接口，用于和电脑或其它网络设备进行以太网数据交换。网络接口芯片采用景略半导体的JL2121工业级GPHY芯片，1路以太网连接到ZYNQ芯片的PS端，1路以太网连接到ZYNQ芯片的PL端。 - HDMI视频输出 1路HDMI视频输出接口，我们选用了ANALOG DEVICE公司的ADV7511 HDMI编码芯片，最高支持1080P@60Hz输出，支持3D输出。 - USB2.0 HOST接口 通过USB Hub芯片扩展4路USB HOST接口，用于连接外部的USB从设备，比如连接鼠标，键盘，U盘等等。USB接口采用扁型USB接口(USB Type A)。 - USB Uart接口 2路Uart转USB接口，用于和电脑通信，方便用户调试。1路在核心板上，核心板独立工作是使用，1路在底板上， 整板调试时使用。串口芯片采用Silicon Labs CP2102GM的USB-UAR芯片, USB接口采用MINI USB接口。 - Micro SD卡座 1路Micro SD卡座，用于存储操作系统镜像和文件系统。 - FMC扩展口 1个标准的FMC LPC的扩展口，可以外接XILINX或者我们黑金的各种FMC模块（HDMI输入输出模块，双目摄像头模块，高速AD模块等等）。FMC扩展口包含34对差分IO信号和一路高速GTX收发信号。 - USB JTAG口 一路USB JTAG口，通过USB线及板载的JTAG电路对ZYNQ系统进行调试和下载 - 时钟 板载一个33.333Mhz的有源晶振，给PS系统提供稳定的时钟源，一个50MHz的有源晶振，为PL逻辑提供额外的时钟；另外板上有一个可编程的时钟芯片给GTX提供时钟源，为PCIE，光纤和DDR工作提供参考时钟。 - LED灯 9个发光二极管LED, 1个电源指示灯；1个DONE配置指示灯；2个串口通信指示灯，1个PS控制LED灯，4个PL控制指示灯。 - 按键 6个按键，1个复位按键，1个PS用户按键，4个PL用户按键。 ZYNQ芯片 ======== 开发板使用的是Xilinx公司的Zynq7000系列的芯片，型号为XC7Z035-2FFG676。芯片的PS系统集成了两个ARM Cortex™-A9处理器，AMBA®互连，内部存储器，外部存储器接口和外设。这些外设主要包括USB总线接口，以太网接口，SD/SDIO接口，I2C总线接口，CAN总线接口，UART接口，GPIO等。PS可以独立运行并在上电或复位下启动。ZYNQ7000芯片的总体框图如图2-1所示 .. image:: images/media/image4.png 图2-1 ZYNQ7000芯片的总体框图 其中PS系统部分的主要参数如下： - 基于ARM 双核CortexA9 的应用处理器，ARM-v7架构 高达800MHz - 每个CPU 32KB 1级指令和数据缓存，512KB 2级缓存 2个CPU共享 - 片上boot ROM和256KB 片内RAM - 外部存储接口，支持16/32 bit DDR2、DDR3接口 - 两个千兆网卡支持：发散-聚集DMA ，GMII，RGMII，SGMII接口 - 两个USB2.0 OTG接口，每个最多支持12节点 - 两个CAN2.0B总线接口 - 两个SD卡、SDIO、MMC兼容控制器 - 2个SPI，2个UARTs，2个I2C接口 - 54个多功能配置的IO，可以软件配置成普通IO或者外设控制接口 - PS内和PS到PL的高带宽连接 其中PL逻辑部分的主要参数如下： - 逻辑单元Logic Cells：275K； - 查找表LUTs: 171,900 - 触发器(flip-flops):343,800 - 乘法器18x25MACCs：900; - Block RAM：17.6Mb； - 8路高速GTX收发器，支持PCIE Gen2x8； - 2个AD转换器,可以测量片上电压、温度感应和高达17外部差分输入通道，1MBPS XC7Z035-2FFG676I芯片的速度等级为-2，工业级，封装为FGG676，引脚间距为1.0mm，ZYNQ7000系列的具体的芯片型号定义如下图2-2所示。 .. image:: images/media/image5.png 图2-2 ZYNQ型号命名规则定义 图2-3为开发板所用的XC7Z035芯片实物图。 .. image:: images/media/image6.png 图2-3 XC7Z035芯片实物 DDR3 DRAM ========= AX7350B开发板上配有四片Micron(美光）的512MB的DDR3芯片,型号为MT41J256M16HA-125(兼容MT41K256M16HA-125)，其中PS和PL端各挂载两片。两片DDR3 SDRAM组成32bit的总线宽度。PS端的DDR3 SDRAM的最高运行速度可达533MHz(数据速率1066Mbps)，两片DDR3存储系统直接连接到了ZYNQ处理系统（PS）的BANK 502的存储器接口上。PL端的DDR3 SDRAM的最高运行速度可达800MHz(数据速率1600Mbps)，两片DDR3存储系统连接到了FPGA的BANK33, BANK34的接口上。DDR3 SDRAM的具体配置如下表3-1所示。 表3-1 DDR3 SDRAM配置 +--------------+---------------------+------------------+--------------+ | **位号** | **芯片型号** | **容量** | **厂家** | +--------------+---------------------+------------------+--------------+ | U4,U5,U7,U8 | MT41J256M16HA-125 | 256M x 16bit | Micron | +--------------+---------------------+------------------+--------------+ DDR3的硬件设计需要严格考虑信号完整性，我们在电路设计和PCB设计的时候已经充分考虑了匹配电阻/终端电阻,走线阻抗控制，走线等长控制，　保证DDR3的高速稳定的工作。 PS端的DDR3 DRAM的硬件连接方式如图3-1所示: .. image:: images/media/image7.png 图3-1 DDR3 DRAM原理图部分 PL端的DDR3 DRAM的硬件连接方式如图3-2所示: .. image:: images/media/image8.png **PS端DDR3 DRAM引脚分配：** +-----------------------+---------------------+------------------------+ | **信号名称** | **ZYNQ引脚名** | **ZYNQ引脚号** | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS0_P** | PS_DDR_DQS_P0_502 | H24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS0_N** | PS_DDR_DQS_N0_502 | G25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS1_P** | PS_DDR_DQS_P1_502 | L24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS1_N** | PS_DDR_DQS_N1_502 | L25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS2_P** | PS_DDR_DQS_P2_502 | P25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS2_N** | PS_DDR_DQS_N2_502 | R25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS3_P** | PS_DDR_DQS_P3_502 | W24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DQS4_N** | PS_DDR_DQS_N3_502 | W25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D0** | PS_DDR_DQ0_502 | J26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D1** | PS_DDR_DQ1_502 | F25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D2** | PS_DDR_DQ2_502 | J25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D3** | PS_DDR_DQ3_502 | G26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D4** | PS_DDR_DQ4_502 | H26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D5** | PS_DDR_DQ5_502 | H23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D6** | PS_DDR_DQ6_502 | J24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D7** | PS_DDR_DQ7_502 | J23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D8** | PS_DDR_DQ8_502 | K26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D9** | PS_DDR_DQ9_502 | L23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D10** | PS_DDR_DQ10_502 | M26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D11** | PS_DDR_DQ11_502 | K23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D12** | PS_DDR_DQ12_502 | M25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D13** | PS_DDR_DQ13_502 | N24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D14** | PS_DDR_DQ14_502 | M24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D15** | PS_DDR_DQ15_502 | N23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D16** | PS_DDR_DQ16_502 | R26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D17** | PS_DDR_DQ17_502 | P24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D18** | PS_DDR_DQ18_502 | N26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D19** | PS_DDR_DQ19_502 | P23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D20** | PS_DDR_DQ20_502 | T24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D21** | PS_DDR_DQ21_502 | T25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D22** | PS_DDR_DQ22_502 | T23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D23** | PS_DDR_DQ23_502 | R23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D24** | PS_DDR_DQ24_502 | V24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D25** | PS_DDR_DQ25_502 | U26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D26** | PS_DDR_DQ26_502 | U24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D27** | PS_DDR_DQ27_502 | U25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D28** | PS_DDR_DQ28_502 | W26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D29** | PS_DDR_DQ29_502 | Y25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D30** | PS_DDR_DQ30_502 | Y26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_D31** | PS_DDR_DQ31_502 | W23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DM0** | PS_DDR_DM0_502 | G24 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DM1** | PS_DDR_DM1_502 | K25 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DM2** | PS_DDR_DM2_502 | P26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_DM3** | PS_DDR_DM3_502 | V26 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A0** | PS_DDR_A0_502 | K22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A1** | PS_DDR_A1_502 | K20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A2** | PS_DDR_A2_502 | N21 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A3** | PS_DDR_A3_502 | L22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A4** | PS_DDR_A4_502 | M20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A5** | PS_DDR_A5_502 | N22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A6** | PS_DDR_A6_502 | L20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A7** | PS_DDR_A7_502 | J21 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A8** | PS_DDR_A8_502 | T20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A9** | PS_DDR_A9_502 | U20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A10** | PS_DDR_A10_502 | M22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A11** | PS_DDR_A11_502 | H21 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A12** | PS_DDR_A12_502 | P20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A13** | PS_DDR_A13_502 | J20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_A14** | PS_DDR_A14_502 | R20 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_BA0** | PS_DDR_BA0_502 | U22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_BA1** | PS_DDR_BA1_502 | T22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_BA2** | PS_DDR_BA2_502 | R22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_S0** | PS_DDR_CS_B_502 | Y21 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_RAS** | PS_DDR_RAS_B_502 | V23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_CAS** | PS_DDR_CAS_B_502 | Y23 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_WE** | PS_DDR_WE_B_502 | V22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_ODT** | PS_DDR_ODT_502 | Y22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_RESET** | PS_DDR_DRST_B_502 | H22 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_CLK0_P** | PS_DDR_CKP_502 | R21 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_CLK0_N** | PS_DDR_CKN_502 | P21 | +-----------------------+---------------------+------------------------+ | **PS_DDR3_CKE** | PS_DDR_CKE_502 | U21 | +-----------------------+---------------------+------------------------+ **PL端DDR3 DRAM引脚分配：** +-----------------------+-----------------------+----------------------+ | **信号名称** | **ZYNQ引脚名** | **ZYNQ引脚号** | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS0_P** | IO_L3P_T0_DQS_33 | G2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS0_N** | IO_L3N_T0_DQS_33 | F2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS1_P** | IO_L9P_T1_DQS_33 | K2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS1_N** | IO_L9N_T1_DQS_33 | K1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS2_P** | IO_L15P_T2_DQS_33 | N3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS2_N** | IO_L15N_T2_DQS_33 | N2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS3_P** | IO_L21P_T3_DQS_33 | M8 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DQS4_N** | IO_L21N_T3_DQS_33 | L8 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D0** | IO_L5N_T0_33 | E1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D1** | IO_L1N_T0_33 | F4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D2** | IO_L4P_T0_33 | D1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D3** | IO_L1P_T0_33 | G4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D4** | IO_L2N_T0_33 | D3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D5** | IO_L5P_T0_33 | E2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D6** | IO_L2P_T0_33 | D4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D7** | IO_L4N_T0_33 | C1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D8** | IO_L7N_T1_33 | H1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D9** | IO_L10N_T1_33 | G1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D10** | IO_L7P_T1_33 | J1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D11** | IO_L8N_T1_33 | H3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D12** | IO_L11N_T1_SRCC_33 | K3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D13** | IO_L8P_T1_33 | H4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D14** | IO_L11P_T1_SRCC_33 | L3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D15** | IO_L10P_T1_33 | H2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D16** | IO_L18P_T2_33 | N1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D17** | IO_L14P_T2_SRCC_33 | L5 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D18** | IO_L14N_T2_SRCC_33 | L4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D19** | IO_L13P_T2_MRCC_33 | M6 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D20** | IO_L16P_T2_33 | M2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D21** | IO_L17P_T2_33 | N4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D22** | IO_L16N_T2_33 | L2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D23** | IO_L17N_T2_33 | M4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D24** | IO_L23P_T3_33 | N7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D25** | IO_L22N_T3_33 | J6 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D26** | IO_L19P_T3_33 | M7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D27** | IO_L20N_T3_33 | J5 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D28** | IO_L24P_T3_33 | K8 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D29** | IO_L20P_T3_33 | K5 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D30** | IO_L24N_T3_33 | K7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_D31** | IO_L22P_T3_33 | K6 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DM0** | IO_L6P_T0_33 | F3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DM1** | IO_L12P_T1_MRCC_33 | J4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DM2** | IO_L13N_T2_MRCC_33 | M5 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_DM3** | IO_L23N_T3_33 | N6 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A0** | IO_L17N_T2_34 | A8 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A1** | IO_L23P_T3_34 | C2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A2** | IO_L14P_T2_SRCC_34 | D6 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A3** | IO_L15N_T2_DQS_34 | B9 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A4** | IO_L10N_T1_34 | D5 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A5** | IO_L17P_T2_34 | A9 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A6** | IO_L11N_T1_SRCC_34 | E7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A7** | IO_L15P_T2_DQS_34 | C9 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A8** | IO_L12N_T1_MRCC_34 | F7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A9** | IO_L18N_T2_34 | A7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A10** | IO_L24N_T3_34 | A2 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A11** | IO_L11P_T1_SRCC_34 | F8 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A12** | IO_L23N_T3_34 | B1 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A13** | IO_L16P_T2_34 | B10 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_A14** | IO_L12P_T1_MRCC_34 | G7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_BA0** | IO_L18P_T2_34 | B7 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_BA1** | IO_L19N_T3_VREF_34 | C3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_BA2** | IO_L22N_T3_34 | A3 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_S0** | IO_L14N_T2_SRCC_34 | C6 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_RAS** | IO_L19P_T3_34 | C4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_CAS** | IO_L20N_T3_34 | B4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_WE** | IO_L20P_T3_34 | B5 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_ODT** | IO_L22P_T3_34 | A4 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_RESET** | IO_L16N_T2_34 | A10 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_CLK0_P** | IO_L21P_T3_DQS_34 | B6 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_CLK0_N** | IO_L21N_T3_DQS_34 | A5 | +-----------------------+-----------------------+----------------------+ | **PL_DDR3_CKE** | IO_L24P_T3_34 | B2 | +-----------------------+-----------------------+----------------------+ QSPI Flash ========== 开发板配有一片256MBit大小的Quad-SPI FLASH芯片，型号为W25Q256FVEI，它使用3.3V CMOS电压标准。由于QSPI FLASH的非易失特性，在使用中， 它可以作为系统的启动设备来存储系统的启动镜像。这些镜像主要包括FPGA的bit文件、ARM的应用程序代码以及其它的用户数据文件。QSPI FLASH的具体型号和相关参数见表4-1。 +--------------+--------------------+------------------+--------------+ | **位号** | **芯片类型** | **容量** | **厂家** | +--------------+--------------------+------------------+--------------+ | U7 | W25Q256FVEI | 32M Byte | Winbond | +--------------+--------------------+------------------+--------------+ 表4-1 QSPI Flash的型号和参数 QSPI FLASH连接到ZYNQ芯片的PS部分BANK500的GPIO口上，在系统设计中需要配置这些PS端的GPIO口功能为QSPI FLASH接口。为图4-1为QSPI Flash在原理图中的部分。 .. image:: images/media/image9.png 图4-1 QSPI Flash连接示意图 **配置芯片引脚分配：** +-----------------------------+------------------+---------------------+ | **信号名称** | **ZYNQ引脚名** | **ZYNQ引脚号** | +-----------------------------+------------------+---------------------+ | **QSPI_SCK** | PS_MIO6_500 | F23 | +-----------------------------+------------------+---------------------+ | **QSPI_CS** | PS_MIO1_500 | D26 | +-----------------------------+------------------+---------------------+ | **QSPI_D0** | PS_MIO2_500 | E25 | +-----------------------------+------------------+---------------------+ | **QSPI_D1** | PS_MIO3_500 | D25 | +-----------------------------+------------------+---------------------+ | **QSPI_D2** | PS_MIO4_500 | F24 | +-----------------------------+------------------+---------------------+ | **QSPI_D3** | PS_MIO5_500 | C26 | +-----------------------------+------------------+---------------------+ eMMC Flash ========== 开发板配有一片大容量的8GB大小的eMMC FLASH芯片，型号为THGBMFG6C1LBAIL，它支持JEDEC e-MMC V5.0标准的HS-MMC接口，电平支持1.8V或者3.3V。eMMC FLASH和ZYNQ连接的数据宽度为4bit。由于eMMC FLASH的大容量和非易失特性，在ZYNQ系统使用中，它可以作为系统大容量的存储设备，比如存储ARM的应用程序、系统文件以及其它的用户数据文件。eMMC FLASH的具体型号和相关参数见表5-1。 +--------------+--------------------+------------------+--------------+ | **位号** | **芯片类型** | **容量** | **厂家** | +--------------+--------------------+------------------+--------------+ | U11 | THGBMFG6C1LBAIL | 8G Byte | TOSHIBA | +--------------+--------------------+------------------+--------------+ 表5-1 eMMC Flash的型号和参数 eMMC FLASH连接到ZYNQ芯片的PS部分BANK501的GPIO口上，在系统设计中需要配置这些PS端的GPIO口功能为SD接口。为图5-1为eMMC Flash在原理图中的部分。 .. image:: images/media/image10.png 图5-1 eMMC Flash连接示意图 **配置芯片引脚分配：** +-----------------------------+------------------+---------------------+ | **信号名称** | **ZYNQ引脚名** | **ZYNQ引脚号** | +-----------------------------+------------------+---------------------+ | **MMC_CCLK** | PS_MIO48_501 | B21 | +-----------------------------+------------------+---------------------+ | **MMC_CMD** | PS_MIO47_501 | B19 | +-----------------------------+------------------+---------------------+ | **MMC_D0** | PS_MIO46_501 | E17 | +-----------------------------+------------------+---------------------+ | **MMC_D1** | PS_MIO49_501 | A18 | +-----------------------------+------------------+---------------------+ | **MMC_D2** | PS_MIO50_501 | B22 | +-----------------------------+------------------+---------------------+ | **MMC_D3** | PS_MIO51_501 | B20 | +-----------------------------+------------------+---------------------+ 时钟配置 ======== AX7350B开发板上分别为PS系统，PL逻辑部分，PL的收发器提供了有源时钟，使PS系统和PL逻辑可以单独工作。 **PS系统时钟源** ZYNQ芯片通过开发板上的X4晶振为PS部分提供33.333MHz的时钟输入。时钟的输入连接到ZYNQ芯片的BANK500的PS_CLK_500的管脚上。其原理图如图6-1所示： .. image:: images/media/image11.png 图6-1 PS部分的有源晶振 **时钟引脚分配：** +-----------------------------------+-----------------------------------+ | **信号名称** | **ZYNQ引脚** | +-----------------------------------+-----------------------------------+ | **PS_CLK** | **B24** | +-----------------------------------+-----------------------------------+ **PL系统时钟源** 板上提供了一个单端50MHz的PL系统时钟源，1.8V供电。晶振输出连接到FPGA BANK35的全局时钟(MRCC)，这个GCLK可以用来驱动FPGA内的用户逻辑电路。该时钟源的原理图如图6-3所示 .. image:: images/media/image12.png 图 6-3 PL系统时钟源 **PL时钟引脚分配：** +-----------------------------------+-----------------------------------+ | **信号名称** | **ZYNQ引脚** | +-----------------------------------+-----------------------------------+ | **CLK_50MHZ** | **J14** | +-----------------------------------+-----------------------------------+ **DDR参考时钟** 一路200Mhz的差分晶振提供给BANK34，作为PL的DDR控制器的参考时钟； .. image:: images/media/image13.png 图 6-5 200Mhz时钟参考源 **PL时钟引脚分配：** +-----------------------------------+-----------------------------------+ | **信号名称** | **ZYNQ引脚** | +-----------------------------------+-----------------------------------+ | CLK0_P | C8 | +-----------------------------------+-----------------------------------+ | CLK0_N | C7 | +-----------------------------------+-----------------------------------+ **收发器参考时钟** 一路156Mhz的差分晶振提供给BANK111，作为GTX收发器的SPF的参考时钟；另外通过DSC557-0334FI1芯片产生2路100Mhz的差分参考时钟分别提供给BANK112和PCIE SOCKET。参考电路设计的示意图如下图所示: .. image:: images/media/image14.png 图 6-6 可编程时钟源 **可编程时钟源ZYNQ引脚分配：** +-----------------------------------+-----------------------------------+ | **信号名称** | **ZYNQ引脚** | +-----------------------------------+-----------------------------------+ | PCIE_CLK0_P | R6 | +-----------------------------------+-----------------------------------+ | PCIE_CLK0_N | R5 | +-----------------------------------+-----------------------------------+ | SFP_CLK0_C_P | AA6 | +-----------------------------------+-----------------------------------+ | SFP_CLK0_C_N | AA5 | +-----------------------------------+-----------------------------------+ USB转串口 ========= 开发板上配备了一个Uart转USB接口，用于核心板单独供电和调试。转换芯片采用Silicon Labs CP2102GM的USB-UAR芯片, USB接口采用MINI USB接口，可以用一根USB线将它连接到上PC的USB口进行核心板的单独供电和串口数据通信 。 USB Uart电路设计的示意图如下图所示: .. image:: images/media/image15.png 7-1 USB转串口示意图 **USB转串口的ZYNQ引脚分配：** +---------------+--------------+------------+-------------------------+ | **信号名称** | **ZY | **ZY | **备注** | | | NQ引脚名** | NQ引脚号** | | +---------------+--------------+------------+-------------------------+ | UART_RXD | PS_MIO13_500 | B25 | Uart数据输入 | +---------------+--------------+------------+-------------------------+ | UART_TXD | PS_MIO12_500 | A23 | Uart数据输出 | +---------------+--------------+------------+-------------------------+ 千兆以太网接口 ============== AX7350B开发板上有2路千兆以太网接口，其中1路以太网接口是连接的PS系统端，另外1路以太网接口是连接到PL的逻辑IO口上。连接到PL端的千兆以太网接口需要通过程序调用IP挂载到ZYNQ的AXI总线系统上。 以太网芯片采用景略半导体的工业级以太网GPHY芯片（JL2121-N040I）为用户提供网络通信服务。PS端的以太网PHY芯片是连接到ZYNQ的PS端BANK501的GPIO接口上。PL端的的以太网PHY芯片是连接到BANK35 的IO上。JL2121芯片支持10/100/1000 Mbps网络传输速率，通过RGMII接口跟Zynq7000系统的MAC层进行数据通信。JL2121D支持ＭDI/MDX自适应，各种速度自适应，Master/Slave自适应，支持MDIO总线进行PHY的寄存器管理。 JL2121上电会检测一些特定的IO的电平状态，从而确定自己的工作模式。表8-1 描述了GPHY芯片上电之后的默认设定信息。 +-----------------+--------------------------+-------------------------+ | **配置Pin脚** | **说明** | **配置值** | +-----------------+--------------------------+-------------------------+ | RXD3_ADR0 | MDIO/MDC 模式的PHY地址 | PHY Address 为 001 | | | | | | RXC_ADR1 | | | | | | | | RXCTL_ADR2 | | | +-----------------+--------------------------+-------------------------+ | RXD1_TXDLY | TX时钟2ns延时 | 延时 | +-----------------+--------------------------+-------------------------+ | RXD0_RXDLY | RX时钟2ns延时 | 延时 | +-----------------+--------------------------+-------------------------+ 表8-1PHY芯片默认配置值 当网络连接到千兆以太网时，ZYNQ和PHY芯片JL2121的数据传输时通过RGMII总线通信，传输时钟为125Mhz，数据在时钟的上升沿和下降样采样。 当网络连接到百兆以太网时，ZYNQ和PHY芯片JL2121的数据传输时通过RMII总线通信，传输时钟为25Mhz。数据在时钟的上升沿和下降样采样。 图8-1为ZYNQ PS端1路以太网PHY芯片连接示意图: |image2|　　　　　　　　　　　　　　　图8-1 ZYNQ PS系统与GPHY连接示意图 图8-2为ZYNQ PL端1路以太网PHY芯片连接示意图: .. image:: images/media/image17.png 图8-2 ZYNQ PL端与GPHY连接示意图 **PS端千兆以太网引脚分配如下：** +-----------------+----------------+-----------------+-----------------+ | **信号名称** | **ZYNQ引脚名** | **ZYNQ引脚号** | **备注** | +-----------------+----------------+-----------------+-----------------+ | **PHY1_TXCK** | PS_MIO16_501 | G21 | RGMII 发送时钟 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_TXD0** | PS_MIO17_501 | G17 | 发送数据bit０ | +-----------------+----------------+-----------------+-----------------+ | **PHY1_TXD1** | PS_MIO18_501 | G20 | 发送数据bit1 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_TXD2** | PS_MIO19_501 | G19 | 发送数据bit2 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_TXD3** | PS_MIO20_501 | H19 | 发送数据bit3 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_TXCTL** | PS_MIO21_501 | F22 | 发送使能信号 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_RXCK** | PS_MIO22_501 | G22 | RGMII接收时钟 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_RXD0** | PS_MIO23_501 | F20 | 接收数据Bit0 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_RXD1** | PS_MIO24_501 | J19 | 接收数据Bit1 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_RXD2** | PS_MIO25_501 | F19 | 接收数据Bit2 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_RXD3** | PS_MIO26_501 | H17 | 接收数据Bit3 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_RXCTL** | PS_MIO27_501 | F18 | 接 | | | | | 收数据有效信号 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_MDC** | PS_MIO52_501 | A20 | MDIO管理时钟 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_MDIO** | PS_MIO53_501 | A19 | MDIO管理数据 | +-----------------+----------------+-----------------+-----------------+ | **PHY1_RESET** | PS_MIO7_500 | E23 | 复位信号 | +-----------------+----------------+-----------------+-----------------+ **PL端千兆以太网引脚分配如下：** +----------------+----------------------+--------------+--------------+ | **信号名称** | **ZYNQ引脚名** | **ZY | **备注** | | | | NQ引脚号** | | +----------------+----------------------+--------------+--------------+ | **PHY2_TXCK** | IO_L4N_T0_35 | D11 | RGMII | | | | | 发送时钟 | +----------------+----------------------+--------------+--------------+ | **PHY2_TXD0** | I | F10 | 发 | | | O_L3N_T0_DQS_AD1N_35 | | 送数据bit０ | +----------------+----------------------+--------------+--------------+ | **PHY2_TXD1** | I | G10 | 发送数据bit1 | | | O_L3P_T0_DQS_AD1P_35 | | | +----------------+----------------------+--------------+--------------+ | **PHY2_TXD2** | IO_L2N_T0_AD8N_35 | D10 | 发送数据bit2 | +----------------+----------------------+--------------+--------------+ | **PHY2_TXD3** | IO_L2P_T0_AD8P_35 | E10 | 发送数据bit3 | +----------------+----------------------+--------------+--------------+ | **PHY2_TXCTL** | IO_L4P_T0_35 | E11 | 发送使能信号 | +----------------+----------------------+--------------+--------------+ | **PHY2_RXCK** | IO_L11P_T1_SRCC_35 | G14 | R | | | | | GMII接收时钟 | +----------------+----------------------+--------------+--------------+ | **PHY2_RXD0** | IO_L6P_T0_35 | F13 | 接收数据Bit0 | +----------------+----------------------+--------------+--------------+ | **PHY2_RXD1** | IO_L1P_T0_AD0P_35 | F12 | 接收数据Bit1 | +----------------+----------------------+--------------+--------------+ | **PHY2_RXD2** | IO_L1N_T0_AD0N_35 | E12 | 接收数据Bit2 | +----------------+----------------------+--------------+--------------+ | **PHY2_RXD3** | IO_L5N_T0_AD9N_35 | G11 | 接收数据Bit3 | +----------------+----------------------+--------------+--------------+ | **PHY2_RXCTL** | IO_L6N_T0_VREF_35 | E13 | 接收 | | | | | 数据有效信号 | +----------------+----------------------+--------------+--------------+ | **PHY2_MDC** | IO_0_VRN_35 | H16 | MDIO管理时钟 | +----------------+----------------------+--------------+--------------+ | **PHY2_MDIO** | IO_L7P_T1_AD2P_35 | H13 | MDIO管理数据 | +----------------+----------------------+--------------+--------------+ | **PHY2_RESET** | IO_L7N_T1_AD2N_35 | H12 | 复位信号 | +----------------+----------------------+--------------+--------------+ USB2.0 Host接口 =============== AX7350B开发板上有4个USB2.0 HOST接口，USB2.0收发器采用的是一个1.8V的，高速的支持ULPI标准接口的USB3320C-EZK芯片，再通过一个USB HUB芯片USB2514扩展出4路USB HOST接口。ZYNQ的USB总线接口和USB3320C-EZK收发器相连接，实现高速的USB2.0 Host模式的数据通信。USB3320C的USB的数据和控制信号连接到ZYNQ芯片PS端的BANK501的IO口上，USB接口差分信号(DP/DM)连接到USB2514芯片扩展出4个USB接口。2个24MHz的晶振为分别为USB3320C和USB2514芯片提供时钟。 4个USB接口为扁型USB接口(USB Type A)，方便用户同时连接不同的USB Slave外设(比如USB鼠标和USB键盘），每个USB接口提供了+5V的电源。 ZYNQ处理器和USB3320C-EZK芯片及USB2514芯片连接的示意图如9-1所示： .. image:: images/media/image18.png 图9-1 Zynq7000和USB芯片间连接示意图 **USB2.0引脚分配：** +---------------+--------------+------------+-------------------------+ | **信号名称** | **ZY | **ZY | **备注** | | | NQ引脚名** | NQ引脚号** | | +---------------+--------------+------------+-------------------------+ | OTG_DATA4 | PS_MIO28_501 | J18 | USB数据Bit4 | +---------------+--------------+------------+-------------------------+ | OTG_DIR | PS_MIO29_501 | E20 | USB数据方向信号 | +---------------+--------------+------------+-------------------------+ | OTG_STP | PS_MIO30_501 | K19 | USB停止信号 | +---------------+--------------+------------+-------------------------+ | OTG_NXT | PS_MIO31_501 | E21 | USB下一数据信号 | +---------------+--------------+------------+-------------------------+ | OTG_DATA0 | PS_MIO32_501 | K17 | USB数据Bit0 | +---------------+--------------+------------+-------------------------+ | OTG_DATA1 | PS_MIO33_501 | E22 | USB数据Bit1 | +---------------+--------------+------------+-------------------------+ | OTG_DATA2 | PS_MIO34_501 | J16 | USB数据Bit2 | +---------------+--------------+------------+-------------------------+ | OTG_DATA3 | PS_MIO35_501 | D19 | USB数据Bit3 | +---------------+--------------+------------+-------------------------+ | OTG_CLK | PS_MIO36_501 | K16 | USB时钟信号 | +---------------+--------------+------------+-------------------------+ | OTG_DATA5 | PS_MIO37_501 | D20 | USB数据Bit5 | +---------------+--------------+------------+-------------------------+ | OTG_DATA6 | PS_MIO38_501 | D21 | USB数据Bit6 | +---------------+--------------+------------+-------------------------+ | OTG_DATA7 | PS_MIO39_501 | C21 | USB数据Bit7 | +---------------+--------------+------------+-------------------------+ | OTG_RESETN | PS_MIO8_500 | A24 | USB复位信号 | +---------------+--------------+------------+-------------------------+ HDMI输出接口 ============ HDMI输出接口的实现，是选用ANALOG DEVICE公司的ADV7511 HDMI（DVI）编码芯片，最高支持1080P@60Hz输出，支持3D输出。 其中，ADV7511的视频数字接口，音频数字接口和I2C配置接口和ZYNQ7000 PL部分的BANK35 IO相连，ZYNQ7000系统通过I2C管脚来对ADV7511进行初始化和控制操作。ADV7511芯片和ZYNQ7000的硬件连接示意图如下图10-1所示： .. image:: images/media/image19.png 图10-1 HDMI接口设计原理图 **ZYNQ的引脚分配：** +----------------+-------------------------+------+-------------------+ | **信号名称** | **ZYNQ引脚名** | **ZY | **备注** | | | | NQ | | | | | 引脚 | | | | | 号** | | +----------------+-------------------------+------+-------------------+ | **HDMI_CLK** | IO_L8P_T1_AD10P_35 | K13 | HDMI视频信号时钟 | +----------------+-------------------------+------+-------------------+ | **HDMI_HSYNC** | IO_L23P_T3_35 | C11 | H | | | | | DMI视频信号行同步 | +----------------+-------------------------+------+-------------------+ | **HDMI_VSYNC** | IO_L22N_T3_AD7N_35 | B12 | H | | | | | DMI视频信号列同步 | +----------------+-------------------------+------+-------------------+ | **HDMI_DE** | IO_L9P_T1_DQS_AD3P_35 | K15 | HDMI视频信号有效 | +----------------+-------------------------+------+-------------------+ | **HDMI_D0** | IO_L10P_T1_AD11P_35 | G16 | HDMI视频信号数据0 | +----------------+-------------------------+------+-------------------+ | **HDMI_D1** | IO_L16P_T2_35 | E16 | HDMI视频信号数据1 | +----------------+-------------------------+------+-------------------+ | **HDMI_D2** | IO_L9N_T1_DQS_AD3N_35 | J15 | HDMI视频信号数据2 | +----------------+-------------------------+------+-------------------+ | **HDMI_D3** | IO_L14N_T2_AD4N_SRCC_35 | E15 | HDMI视频信号数据3 | +----------------+-------------------------+------+-------------------+ | **HDMI_D4** | IO_L14P_T2_AD4P_SRCC_35 | F15 | HDMI视频信号数据4 | +----------------+-------------------------+------+-------------------+ | **HDMI_D5** | IO_L10N_T1_AD11N_35 | G15 | HDMI视频信号数据5 | +----------------+-------------------------+------+-------------------+ | **HDMI_D6** | IO_L11N_T1_SRCC_35 | F14 | HDMI视频信号数据6 | +----------------+-------------------------+------+-------------------+ | **HDMI_D7** | IO_L12N_T1_MRCC_35 | H14 | HDMI视频信号数据7 | +----------------+-------------------------+------+-------------------+ | **HDMI_D8** | IO_L8N_T1_AD10N_35 | J13 | HDMI视频信号数据8 | +----------------+-------------------------+------+-------------------+ | **HDMI_D9** | IO_25_VRP_35 | K12 | HDMI视频信号数据9 | +----------------+-------------------------+------+-------------------+ | **HDMI_D10** | IO_L23N_T3_35 | B11 | H | | | | | DMI视频信号数据10 | +----------------+-------------------------+------+-------------------+ | **HDMI_D11** | IO_L22P_T3_AD7P_35 | C12 | H | | | | | DMI视频信号数据11 | +----------------+-------------------------+------+-------------------+ | **HDMI_D12** | IO_L19P_T3_35 | D13 | H | | | | | DMI视频信号数据12 | +----------------+-------------------------+------+-------------------+ | **HDMI_D13** | IO_L24N_T3_AD15N_35 | A12 | H | | | | | DMI视频信号数据13 | +----------------+-------------------------+------+-------------------+ | **HDMI_D14** | IO_L19N_T3_VREF_35 | C13 | H | | | | | DMI视频信号数据14 | +----------------+-------------------------+------+-------------------+ | **HDMI_D15** | IO_L24P_T3_AD15P_35 | A13 | H | | | | | DMI视频信号数据15 | +----------------+-------------------------+------+-------------------+ | **HDMI_D16** | IO_L13N_T2_MRCC_35 | D14 | H | | | | | DMI视频信号数据16 | +----------------+-------------------------+------+-------------------+ | **HDMI_D17** | IO_L13P_T2_MRCC_35 | D15 | H | | | | | DMI视频信号数据17 | +----------------+-------------------------+------+-------------------+ | **HDMI_D18** | IO_L21N_T3_DQS_AD14N_35 | A14 | H | | | | | DMI视频信号数据18 | +----------------+-------------------------+------+-------------------+ | **HDMI_D19** | IO_L20N_T3_AD6N_35 | B14 | H | | | | | DMI视频信号数据19 | +----------------+-------------------------+------+-------------------+ | **HDMI_D20** | IO_L21P_T3_DQS_AD14P_35 | A15 | H | | | | | DMI视频信号数据20 | +----------------+-------------------------+------+-------------------+ | **HDMI_D21** | IO_L17N_T2_AD5N_35 | B15 | H | | | | | DMI视频信号数据21 | +----------------+-------------------------+------+-------------------+ | **HDMI_D22** | IO_L16N_T2_35 | D16 | H | | | | | DMI视频信号数据22 | +----------------+-------------------------+------+-------------------+ | **HDMI_D23** | IO_L17P_T2_AD5P_35 | B16 | H | | | | | DMI视频信号数据23 | +----------------+-------------------------+------+-------------------+ | **HDMI_SPDIF** | IO_L20P_T3_AD6P_35 | C14 | H | | | | | DMI音频S/PDIF输入 | +----------------+-------------------------+------+-------------------+ | **H | IO_L18P_T2_AD13P_35 | B17 | H | | DMI_SPDIFOUT** | | | DMI音频S/PDIF输出 | +----------------+-------------------------+------+-------------------+ | **HDMI_INT** | IO_L15P_T2_DQS_AD12P_35 | C17 | HDMI中断信号 | +----------------+-------------------------+------+-------------------+ | **HDMI_SCL** | IO_L18N_T2_AD13N_35 | A17 | HDMI IIC控制时钟 | +----------------+-------------------------+------+-------------------+ | **HDMI \_SDA** | IO_L15N_T2_DQS_AD12N_35 | C16 | HDMI IIC控制数据 | +----------------+-------------------------+------+-------------------+ 光纤接口 ======== AX7350B开发板上有2路光纤接口，用户可以购买SFP光模块(市场上1.25G，2.5G，10G光模块）插入到这2个光纤接口中进行光纤数据通信。2路光纤接口分别跟ZYNQ的BANK111的GTX收发器的2路RX/TX相连接，TX信号和RX信号都是以差分信号方式通过隔直电容连接ZYNQ和光模块，每路TX发送和RX接收数据速率高达10Gb/s。BANK111的GTX收发器的参考时钟由是156.25Mhz差分晶振提供。 FPGA和光纤设计示意图如下图11-1所示: .. image:: images/media/image20.png 图11-1光纤设计示意图 **第1路光纤接口ZYNQ引脚分配如下：** +------------------+----------------+---------------------------------+ | **网络名称** | **ZYNQ引脚** | **备注** | +------------------+----------------+---------------------------------+ | **SFP1_TX_P** | AF4 | SFP光模块数据发送 Positive | +------------------+----------------+---------------------------------+ | **SFP1_TX_N** | AF3 | SFP光模块数据发送Negative | +------------------+----------------+---------------------------------+ | **SFP1_RX_P** | AE6 | SFP光模块数据接收 Positive | +------------------+----------------+---------------------------------+ | **SFP1_RX_P** | AE5 | SFP光模块数据接收Negative | +------------------+----------------+---------------------------------+ | ** | AA14 | SFP光模块光发射禁止，高有效 | | SFP1_TX_DIS_LS** | | | +------------------+----------------+---------------------------------+ | **SFP1_LOSS_LS** | W16 | SFP光接收L | | | | OSS信号，高表示没有接收到光信号 | +------------------+----------------+---------------------------------+ .. **第2路光纤接口ZYNQ引脚分配如下：** +------------------+----------------+---------------------------------+ | **网络名称** | **ZYNQ引脚** | **备注** | +------------------+----------------+---------------------------------+ | **SFP2_TX_P** | AE2 | SFP光模块数据发送 Positive | +------------------+----------------+---------------------------------+ | **SFP2_TX_N** | AE1 | SFP光模块数据发送Negative | +------------------+----------------+---------------------------------+ | **SFP2_RX_P** | AC6 | SFP光模块数据接收 Positive | +------------------+----------------+---------------------------------+ | **SFP2_RX_P** | AC5 | SFP光模块数据接收Negative | +------------------+----------------+---------------------------------+ | ** | Y16 | SFP光模块光发射禁止，高有效 | | SFP2_TX_DIS_LS** | | | +------------------+----------------+---------------------------------+ | **SFP2_LOSS_LS** | W15 | SFP光接收L | | | | OSS信号，高表示没有接收到光信号 | +------------------+----------------+---------------------------------+ PCIe插槽 ======== AX7350B开发板上有一个PCIe的插槽，在物理上可以连接PCIe的板卡。在电气连接上我们只有4对收发器连接到PCIEx8的插槽上，所以只能实现PCIEex4, PCIex2, PCIex1的数据通信。 PCIe接口的收发信号直接跟ZYNQ BANK112的GTX收发器相连接，4路TX信号和RX信号都是以差分信号方式连接到BANK112，单通道通信速率可高达5G bit带宽。PCIe插槽的参考时钟由时钟芯片SI5338P提供，参考时钟频率为100Mhz。 开发板的PCIe接口的设计示意图如下图12-1所示,其中TX发送信号用AC耦合模式连接。 .. image:: images/media/image21.png 图12-1 PCIe插槽设计示意图 **PCIe x4接口FPGA引脚分配如下：** +------------------+----------------+---------------------------------+ | **网络名称** | **FPGA引脚** | **备注** | +------------------+----------------+---------------------------------+ | PCIE_RX0_P | AB4 | PCIE通道0数据接收 Positive | +------------------+----------------+---------------------------------+ | PCIE_RX0_N | AB3 | PCIE通道0数据接收Negative | +------------------+----------------+---------------------------------+ | PCIE_RX1_P | Y4 | PCIE通道1数据接收 Positive | +------------------+----------------+---------------------------------+ | PCIE_RX1_N | Y3 | PCIE通道1数据接收Negative | +------------------+----------------+---------------------------------+ | PCIE_RX2_P | V4 | PCIE通道2数据接收 Positive | +------------------+----------------+---------------------------------+ | PCIE_RX2_N | V3 | PCIE通道2数据接收Negative | +------------------+----------------+---------------------------------+ | PCIE_RX3_P | T4 | PCIE通道3数据接收 Positive | +------------------+----------------+---------------------------------+ | PCIE_RX3_N | T3 | PCIE通道3数据接收Negative | +------------------+----------------+---------------------------------+ | PCIE_TX0_P | AA2 | PCIE通道0数据发送 Positive | +------------------+----------------+---------------------------------+ | PCIE_TX0_N | AA1 | PCIE通道0数据发送Negative | +------------------+----------------+---------------------------------+ | PCIE_TX1_P | W2 | PCIE通道1数据发送 Positive | +------------------+----------------+---------------------------------+ | PCIE_TX1_N | W1 | PCIE通道1数据发送Negative | +------------------+----------------+---------------------------------+ | PCIE_TX2_P | U2 | PCIE通道2数据发送 Positive | +------------------+----------------+---------------------------------+ | PCIE_TX2_N | U1 | PCIE通道2数据发送Negative | +------------------+----------------+---------------------------------+ | PCIE_TX3_P | R2 | PCIE通道3数据发送 Positive | +------------------+----------------+---------------------------------+ | PCIE_TX3_N | R1 | PCIE通道3数据发送Negative | +------------------+----------------+---------------------------------+ | PCIE_PERST_LS | AA19 | PCIE板卡的复位信号 | +------------------+----------------+---------------------------------+ | PCIE_PRSNT_LS | AA18 | PCIE板卡的存在指示信号 | +------------------+----------------+---------------------------------+ SD卡槽 ====== AX7350B开发板包含了一个Micro型的SD卡接口，以提供用户访问SD卡存储器，用于存储ZYNQ芯片的BOOT程序，Linux操作系统内核, 文件系统以及其它的用户数据文件。 SDIO信号与ZYNQ的PS BANK501的IO信号相连，因为该BANK的VCCIO设置为1.8V，但SD卡的数据电平为3.3V, 我们这里通过TXS02612电平转换器来连接。Zynq7000 PS和SD卡连接器的原理图如图13-1所示。 .. image:: images/media/image22.png 图13-1 SD卡连接示意图 **SD卡槽引脚分配** +---------------+--------------+------------+-------------------------+ | **信号名称** | **ZY | **ZY | **备注** | | | NQ引脚名** | NQ引脚号** | | +---------------+--------------+------------+-------------------------+ | SD_CLK | PS_MIO40 | C22 | SD时钟信号 | +---------------+--------------+------------+-------------------------+ | SD_CMD | PS_MIO41 | C19 | SD命令信号 | +---------------+--------------+------------+-------------------------+ | SD_D0 | PS_MIO42 | F17 | SD数据Data0 | +---------------+--------------+------------+-------------------------+ | SD_D1 | PS_MIO43 | D18 | SD数据Data1 | +---------------+--------------+------------+-------------------------+ | SD_D2 | PS_MIO44 | E18 | SD数据Data2 | +---------------+--------------+------------+-------------------------+ | SD_D3 | PS_MIO45 | C18 | SD数据Data3 | +---------------+--------------+------------+-------------------------+ | SD_CD | PS_MIO10 | A25 | SD卡插入信号 | +---------------+--------------+------------+-------------------------+ FMC连接器 ========= AX7350B开发板带有一个标准的FMC LPC的扩展口，可以外接XILINX或者我们黑金的各种FMC模块（HDMI输入输出模块，双目摄像头模块，高速AD模块等等）。FMC扩展口包含34对差分IO信号和一路高速GTX收发信号。 FMC扩展口的33对差分信号连接到ZYNQ芯片的BANK12, BANK13的IO上，BANK12和BANK13的IO电平标准是由BANK的电压VADJ决定的，默认为2.5V，使34对差分信号支持LVDS数据通信。另外一路GTX收发信号和参考时钟信号分别连接到ZYNQ BANK111的GTX收发器和时钟输入。Zynq7000和FMC连接器的原理图如图14-1所示。 .. image:: images/media/image23.png 图14-1 FMC连接器连接示意图 **FMC连接器引脚分配** +---------------+-------------------+-------+-------------------------+ | **信号名称** | **ZYNQ引脚名** | **ZYN | **备注** | | | | Q引脚 | | | | | 号** | | +---------------+-------------------+-------+-------------------------+ | FMC_CLK0_P | I | AC13 | FMC参考第1路参考时钟P | | | O_L12P_T1_MRCC_12 | | | +---------------+-------------------+-------+-------------------------+ | FMC_CLK0_N | I | AD13 | FMC参考第1路参考时钟N | | | O_L12N_T1_MRCC_12 | | | +---------------+-------------------+-------+-------------------------+ | FMC_CLK1_P | I | AD20 | FMC参考第2路参考时钟P | | | O_L13P_T2_MRCC_13 | | | +---------------+-------------------+-------+-------------------------+ | FMC_CLK1_N | I | AD21 | FMC参考第2路参考时钟N | | | O_L13N_T2_MRCC_13 | | | +---------------+-------------------+-------+-------------------------+ | FMC_LA00_CC_P | I | AC14 | FM | | | O_L13P_T2_MRCC_12 | | C参考第0路数据（时钟）P | +---------------+-------------------+-------+-------------------------+ | FMC_LA00_CC_N | I | AD14 | FM | | | O_L13N_T2_MRCC_12 | | C参考第0路数据（时钟）N | +---------------+-------------------+-------+-------------------------+ | FMC_LA01_CC_P | I | AB15 | FM | | | O_L14P_T2_SRCC_12 | | C参考第1路数据（时钟）P | +---------------+-------------------+-------+-------------------------+ | FMC_LA01_CC_N | I | AB14 | FM | | | O_L14N_T2_SRCC_12 | | C参考第1路数据（时钟）N | +---------------+-------------------+-------+-------------------------+ | FMC_LA02_P | IO_L3P_T0_DQS_12 | Y10 | FMC参考第2路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA02_N | IO_L3N_T0_DQS_12 | AA10 | FMC参考第2路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA03_P | IO_L17P_T2_12 | AE16 | FMC参考第3路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA03_N | IO_L17N_T2_12 | AE15 | FMC参考第3路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA04_P | IO_L7P_T1_12 | AE10 | FMC参考第4路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA04_N | IO_L7N_T1_12 | AD10 | FMC参考第4路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA05_P | I | AC12 | FMC参考第5路数据P | | | O_L11P_T1_SRCC_12 | | | +---------------+-------------------+-------+-------------------------+ | FMC_LA05_N | I | AD11 | FMC参考第5路数据N | | | O_L11N_T1_SRCC_12 | | | +---------------+-------------------+-------+-------------------------+ | FMC_LA06_P | IO_L9P_T1_DQS_12 | AE11 | FMC参考第6路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA06_N | IO_L9N_T1_DQS_12 | AF10 | FMC参考第6路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA07_P | IO_L4P_T0_12 | AB11 | FMC参考第7路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA07_N | IO_L4N_T0_12 | AB10 | FMC参考第7路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA08_P | IO_L1P_T0_12 | Y12 | FMC参考第8路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA08_N | IO_L1N_T0_12 | Y11 | FMC参考第8路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA09_P | IO_L10P_T1_12 | AE13 | FMC参考第9路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA09_N | IO_L10N_T1_12 | AF13 | FMC参考第9路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA10_P | IO_L2P_T0_12 | AB12 | FMC参考第10路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA10_N | IO_L2N_T0_12 | AC11 | FMC参考第10路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA11_P | IO_L8P_T1_12 | AE12 | FMC参考第11路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA11_N | IO_L8N_T1_12 | AF12 | FMC参考第11路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA12_P | IO_L5P_T0_12 | W13 | FMC参考第12路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA12_N | IO_L5N_T0_12 | Y13 | FMC参考第12路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA13_P | IO_L15P_T2_DQS_12 | AD16 | FMC参考第13路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA13_N | IO_L15N_T2_DQS_12 | AD15 | FMC参考第13路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA14_P | IO_L16P_T2_12 | AF15 | FMC参考第14路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA14_N | IO_L16N_T2_12 | AF14 | FMC参考第14路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA15_P | IO_L18P_T2_12 | AE17 | FMC参考第15路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA15_N | IO_L18N_T2_12 | AF17 | FMC参考第15路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA16_P | IO_L20P_T3_12 | AB17 | FMC参考第16路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA16_N | IO_L20N_T3_12 | AB16 | FMC参考第16路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA17_CC_P | I | AC23 | FMC | | | O_L12P_T1_MRCC_13 | | 参考第17路数据（时钟）P | +---------------+-------------------+-------+-------------------------+ | FMC_LA17_CC_N | I | AC24 | FMC | | | O_L12N_T1_MRCC_13 | | 参考第17路数据（时钟）N | +---------------+-------------------+-------+-------------------------+ | FMC_LA18_CC_P | I | AD23 | FMC | | | O_L11P_T1_SRCC_13 | | 参考第18路数据（时钟）P | +---------------+-------------------+-------+-------------------------+ | FMC_LA18_CC_N | I | AD24 | FMC | | | O_L11N_T1_SRCC_13 | | 参考第18路数据（时钟）N | +---------------+-------------------+-------+-------------------------+ | FMC_LA19_P | IO_L16P_T2_13 | AE20 | FMC参考第19路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA19_N | IO_L16N_T2_13 | AE21 | FMC参考第19路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA20_P | IO_L15P_T2_DQS_13 | AF19 | FMC参考第20路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA20_N | IO_L15N_T2_DQS_13 | AF20 | FMC参考第20路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA21_P | IO_L20P_T3_13 | AA20 | FMC参考第21路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA21_N | IO_L20N_T3_13 | AB20 | FMC参考第21路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA22_P | IO_L17P_T2_13 | AD18 | FMC参考第22路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA22_N | IO_L17N_T2_13 | AD19 | FMC参考第22路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA23_P | IO_L18P_T2_13 | AE18 | FMC参考第23路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA23_N | IO_L18N_T2_13 | AF18 | FMC参考第23路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA24_P | IO_L8P_T1_13 | AE23 | FMC参考第24路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA24_N | IO_L8N_T1_13 | AF23 | FMC参考第24路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA25_P | IO_L9P_T1_DQS_13 | AB21 | FMC参考第25路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA25_N | IO_L9N_T1_DQS_13 | AB22 | FMC参考第25路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA26_P | IO_L7P_T1_13 | AE22 | FMC参考第26路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA26_N | IO_L7N_T1_13 | AF22 | FMC参考第26路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA27_P | I | AC21 | FMC参考第27路数据P | | | O_L14P_T2_SRCC_13 | | | +---------------+-------------------+-------+-------------------------+ | FMC_LA27_N | I | AC22 | FMC参考第27路数据N | | | O_L14N_T2_SRCC_13 | | | +---------------+-------------------+-------+-------------------------+ | FMC_LA28_P | IO_L10P_T1_13 | AA22 | FMC参考第28路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA28_N | IO_L10N_T1_13 | AA23 | FMC参考第28路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA29_P | IO_L5P_T0_13 | AF24 | FMC参考第29路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA29_N | IO_L5N_T0_13 | AF25 | FMC参考第29路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA30_P | IO_L4P_T0_13 | AD25 | FMC参考第30路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA30_N | IO_L4N_T0_13 | AD26 | FMC参考第30路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA31_P | IO_L3P_T0_DQS_13 | AE25 | FMC参考第31路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA31_N | IO_L3N_T0_DQS_13 | AE26 | FMC参考第31路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA32_P | IO_L2P_T0_13 | AB26 | FMC参考第32路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA32_N | IO_L2N_T0_13 | AC26 | FMC参考第32路数据N | +---------------+-------------------+-------+-------------------------+ | FMC_LA33_P | IO_L1P_T0_13 | AA25 | FMC参考第33路数据P | +---------------+-------------------+-------+-------------------------+ | FMC_LA33_N | IO_L1N_T0_13 | AB25 | FMC参考第33路数据N | +---------------+-------------------+-------+-------------------------+ LED灯 ===== AX7350B开发板上有9个发光二极管LED, 1个电源指示灯；1个DONE配置指示灯；2个串口通信指示灯，1个PS控制LED灯，4个PL控制指示灯。当开发板上电后电源指示灯会亮起；当FPGA 配置程序后，配置LED灯会亮起。1个用户LED灯一个连接到PS的MIO上，4个LED灯连接到PL的IO上，用户可以通过程序来控制亮和灭，当连接用户LED灯的IO电压为低时，用户LED灯熄灭，当连接IO电压为高时，用户LED会被点亮。因为BANK34的电平为1.5V，这里我们增加了三级管来驱动LED的亮灭。用户LED灯硬件连接的示意图如图15-1所示： .. image:: images/media/image24.png 图15-1用户LED灯硬件连接示意图 **用户LED灯的引脚分配** +--------------+------------------+--------------+--------------------+ | **信号名称** | **ZYNQ引脚名** | **ZY | **备注** | | | | NQ管脚号** | | +--------------+------------------+--------------+--------------------+ | MIO0_LED | PS_MIO0_500 | E26 | 用户PS LED灯 | +--------------+------------------+--------------+--------------------+ | PL_LED1 | IO_L7P_T1_34 | F5 | 用户PL LED1灯 | +--------------+------------------+--------------+--------------------+ | PL_LED2 | IO_L7N_T1_34 | E5 | 用户PL LED2灯 | +--------------+------------------+--------------+--------------------+ | PL_LED3 | O_L2N_T0_34 | G5 | 用户PL LED3灯 | +--------------+------------------+--------------+--------------------+ | PL_LED4 | IO_L2P_T0_34 | G6 | 用户PL LED4灯 | +--------------+------------------+--------------+--------------------+ 复位按键和用户按键 ================== AX7350B开发板上有1个复位按键RESET和5个用户按键。复位信号连接到ZYNQ芯片PS复位管脚上，用户可以使用这个复位按键来复位ZYNQ系统，5个用户按键中1个按键是连接到PS的IO上，另外4个按键是连接到PL的IO上。复位按键和用户按键都是低电平有效，复位按键和用户按键的连接示意图如图16-1所示： .. image:: images/media/image25.png 图16-1 复位按键连接示意图 **按键的ZYNQ管脚分配** +--------------+------------------+------------+-----------------------+ | **信号名称** | **ZYNQ引脚名** | **ZY | **备注** | | | | NQ引脚号** | | +--------------+------------------+------------+-----------------------+ | PS_POR_B | PS_POR_B_500 | C23 | ZYNQ系统复位信号 | +--------------+------------------+------------+-----------------------+ | PS_KEY | PS_MIO11_500 | B26 | PS按键输入 | +--------------+------------------+------------+-----------------------+ | PL_KEY1 | IO_L4N_T0_34 | H6 | PL按键1输入 | +--------------+------------------+------------+-----------------------+ | PL_KEY2 | IO_L4P_T0_34 | H7 | PL按键2输入 | +--------------+------------------+------------+-----------------------+ | PL_KEY3 | I | H8 | PL按键3输入 | | | O_L6N_T0_VREF_34 | | | +--------------+------------------+------------+-----------------------+ | PL_KEY4 | IO_L6P_T0_34 | J8 | PL按键4输入 | +--------------+------------------+------------+-----------------------+ JTAG调试口 ========== 在AX7350B开发板上已经集成了JTAG的下载调试电路，所以用户无需购买额外的Xilinx下载器。只要一根USB线就能进行ZYNQ的开发和调试了。在开发板上通过一个FTDI的USB桥接芯片FT232HL实现PC的USB和ZYNQ的JTAG调试信号TCK,TDO,TMS,TDI进行数据通信。图17-1为开发板上JTAG口的原理图部分： .. image:: images/media/image26.png 图17-1 原理图中JTAG接口部分 在AX7350B开发板上，JTAG接口的形式是USB接口方式的，用户可以通过我们提供的USB线连接PC和JTAG接口进行ZYNQ的系统调试。 拨码开关配置 ============ 开发板上有一个2位的拨码开关SW1用来配置ZYNQ系统的启动模式。AX7350B系统开发平台支持三种启动模式。这三种启动模式分别是JTAG调试模式, QSPI FLASH和SD卡启动模式。XC7Z035芯片上电后会检测响应MIO口（MIO5和MIO4）的电平来决定那种启动模式。用户可以通过核心板上的拨码开关SW1来选择不同的启动模式。SW1启动模式配置如下表18-1所示。 +--------------------+----------------+----------------+---------------+ | **SW1** | **拨码 | **M | **启动模式** | | | 位置（1，2）** | IO5,MIO4电平** | | +--------------------+----------------+----------------+---------------+ | |image3| | ON、ON | 0、0 | JTAG | +--------------------+----------------+----------------+---------------+ | | OFF、OFF | 1、1 | SD卡 | +--------------------+----------------+----------------+---------------+ | | OFF、ON | 1、0 | QSPI FLASH | +--------------------+----------------+----------------+---------------+ 表18-1 SW1启动模式配置 电源 ==== 开发板的电源输入电压为DC12V，外接+12V电源给板子供电。外接电源供电时请使用开发板自带的电源,不要用其他规格的电源，以免损坏开发板。+12V输入电源通过DCDC电源芯片MYMGK1R820ERSR产生+1.0V的FPGA核心电源，MYMGK1R820ERSR输出电流高达20A，满足FPGA的核心电压的电流需求。另外+12V通过DC/DC电源芯片ETA8156FT2G产生+1.5V，通过DCDC芯片ETA1471FT2G来产生其它的电源。DDR3的VTT和VREF电压由TPS51200芯片来产生。 板上的电源设计示意图如下图19-1所示: .. image:: images/media/image28.png 图19-1原理图中电源接口部分 各个电源分配的功能如下表所示： +----------------------+-----------------------------------------------+ | **电源** | **功能** | +----------------------+-----------------------------------------------+ | +1.0V | ZYNQ PS和PL部分的内核电压 | +----------------------+-----------------------------------------------+ | +1.8V | ZYNQ PS和PL部分辅助电压，BANK501 | | | IO电压，eMMC，HDMI | +----------------------+-----------------------------------------------+ | +3.3V | ZYNQ Bank0,Bank500，QSIP FLASH, Clock晶振, | | | SD卡，SFP光模块 | +----------------------+-----------------------------------------------+ | +1.5V | DDR3, ZYNQ Bank501, Bank33,Bank34 | +----------------------+-----------------------------------------------+ | +1.2V | 千兆以太网 | +----------------------+-----------------------------------------------+ | VADJ(+2.5V) | ZYNQ Bank12, Bank13, FMC | +----------------------+-----------------------------------------------+ | VREF, VTT（+0.75V） | PS DDR3，PL DDR3 | +----------------------+-----------------------------------------------+ | MGTAVCC(+1.0V) | ZYNQ Bank111, Bank112 | +----------------------+-----------------------------------------------+ | MGTAVTT(+1.2V) | ZYNQ Bank111, Bank112 | +----------------------+-----------------------------------------------+ 因为ZYNQ FPGA的电源有上电顺序的要求，在电路设计中，我们已经按照 芯片的电源要求设计，上电依次为+1.0V->+1.8V->（+1.5 V、+3.3V、VCCIO）的电路设计，保证芯片的正常工作。 风扇 ==== 因为ZYNQ 7Z035正常工作时会产生大量的热量，我们在板上为芯片增加了一个散热片和风扇，防止芯片过热。风扇的控制由ZYNQ芯片来控制，控制管脚连接到BANK34的IO上，如果IO电平输出为低，MOSFET管导通，风扇工作，如果IO电平输出为高，风扇停止。板上的风扇设计图如下图20-1所示: .. image:: images/media/image29.png 图20-1 开发板原理图中风扇设计 风扇出厂前已经用螺丝固定在开发板上，风扇的电源连接到了J22的插座上，红色的为正极，黑色的为负极。 结构尺寸图 ========== .. image:: images/media/image30.png 正面图（Top View） .. |image1| image:: images/media/image1.png .. |image2| image:: images/media/image16.png .. |image3| image:: images/media/image27.png